In the conventional bulk silicon CMOS, a pn junction is formed between the well region and the substrate, while a pn junction is also formed between the source and drain regions and the substrate in the MOSFET. These parasitic controlled silicon structures may cause a high leakage current between the power source and ground under certain conditions, thereby generating a latch-up effect. Especially under the logic circuit technology node of 0.25 μm, such parasitic latch-up effect greatly hinders further improvement of the semiconductor device performance.
One of the methods that can effectively prevent the latch-up effect is to adopt the Shallow Trench Isolation (STI) technique. The parasitic electrical connection that might be formed between the NMOS and PMOS devices can be discontinued by the shallow trench isolation that is insulated and filled with, for example, silicon oxide, thereby increasing the device reliability. In addition, as compared to the local oxidation of silicon process (LOCOS), the STI occupies a shorter width of the channel and has a smaller isolation pitch, thus it will not erode the active region, thereby avoiding the Bird's Beak effect of LOCOS. Moreover, the isolation structures formed by the STI are mostly located under the surface of the substrate, which will facilitate the planarization of the entire surface of the device.
However, the existing STI may accumulate stresses during the formation of the STI, and the accumulated stresses may cause defects, such as dislocation, to the substrate. These defects would be used as the recombination centers of the electron-hole pairs during the operation of the device, thereby increasing the leakage current of the substrate of the device.
Therefore, it is desired to release the stresses accumulated during the formation of the STI so as to avoid the above-mentioned problem.